`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   00:33:15 05/13/2014
// Design Name:   ahb_3_6
// Module Name:   C:/Users/xristos/Desktop/mathimata/earino 13-14/vlsi/ahb_3_6/ahb3_6/ahb3_6/ahb_3_6_tb.v
// Project Name:  ahb3_6
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ahb_3_6
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

`include  "ahb_3_6.v"

`include  "ahb_matrix_3_6.v"
`include  "ahb_matrix_3_6_bus.v"
`include  "ahb_matrix_3_6_dec.v"
`include  "ahb_matrix_3_6_hlast.v"
`include  "ahb_matrix_3_6_sel.v"
`include  "master2.v"
`include  "prgen_arbiter_mstr_3_6.v"


module ahb_3_6_tb;

	// Inputs
	reg clk;
	reg reset;
	// Instantiate the Unit Under Test (UUT)
	ahb_3_6 uut (
		.clk(clk), 
		.reset(reset)
	);

	initial begin
	  $dumpfile("waveform.vcd");
	  $dumpvars(0,ahb_3_6_tb);
		clk = 0;
		reset = 0;
		
		#10;
		reset=1;
		#20;
        
		reset=0; 
		#600 $finish;

	end
	
   always 
   begin
	  #5 clk = ~clk;
   end
      
endmodule

